The present invention relates to a shift register and a display device, and more particularly to a clock-inverter-type shift register constituting of clock(ed) inverters connected to form a multiplicity of stages, and also to an active matrix type display device using such a shift register in a portion of its peripheral driving circuit.
It has been known heretofore that, in a shift register employing a clock inverter, a basic circuit includes a clock inverter where four transistor elements are connected in series between a positive power supply and a negative power supply, and an input pulse is shifted and held synchronously with a clock pulse (e.g., see Patent Reference 1).
[Patent Reference 1]
Japanese Patent Laid-open No. Hei 11-134893 (particularly paragraphs 0018 to 0020, 0023 to 0025, and FIGS. 2 and 4).
Hereinafter a conventional shift register according to the related art will be described concretely reference to the accompanying drawings. FIG. 9 is a circuit diagram showing a circuit structure of one shift stage in the conventional shift register as a known example. As obvious from this diagram, one shift stage is composed of a unit circuit, which forms a pair of clock inverters 101, 102 and a next-stage inverter 103. A plurality of such shift stages are cascade-connected to constitute a shift register.
The clock inverter 101 is composed of a PMOS transistor Qp101 and an NMOS transistor Qn101 whose gates and drains are mutually connected in common respectively to thereby constitute a C-MOS inverter; a PMOS transistor Qp102 connected between the source of the PMOS transistor Qp101 and a positive power supply VDD, and receiving a clock pulse ck1 as a gate input; and an NMOS transistor Qn102 connected between the source of the NMOS transistor Qn101 and a negative power supply VSS, and receiving, as a gate input, a clock pulse ck1x, which is opposite in phase to the clock pulse ck1.
Similarly to the clock inverter 101, the clock inverter 102 is composed of MOS transistors Qp103 and Qn103 whose gates and drains are mutually connected in common respectively to thereby constitute a C-MOS inverter; a PMOS transistor Qp104 connected between the source of the PMOS transistor Qp103 and the positive power supply VDD, and receiving a clock pulse ck1x as a gate input; and an NMOS transistor Qn104 connected between the source of the NMOS transistor Qn103 and the negative power supply VSS, and receiving a clock pulse ck1 as a gate input.
In these clock inverters 101 and 102, the respective output ends are connected to each other, i.e., the drain common joint of the MOS transistors Qp101, Qn101 and the drain common joint of the MOS transistors Qp103, Qn103 are connected mutually. An input pulse st1 is fed to the input end of the clock inverter 101, i.e., to the gate common joint of the MOS transistors Qp101 and Qn101, and an output pulse out1 is obtained from the output end of the clock inverter 102.
The inverter 103 is composed of a PMOS transistor Qp105 and an NMOS transistor Qn105 whose gates and drains are mutually connected in common respectively to thereby constitute a C-MOS inverter. The input end of this inverter 103, i.e., the gate common joint of the MOS transistors Qp105 and Qn105, is connected to the output end of the clock inverter 102. The output end of the inverter 103, i.e., the drain common joint of the MOS transistors Qp103 and Qn103, is connected to the input end of the clock inverter 102, i.e., to the gate common joint of the MOS transistors Qp103 and Qn103.
FIG. 10 shows the timing relationship among the input pulse st1, the clock pulses ck1, ck1x and the output pulse out1. The input pulse st1 is taken into the clock inverter 101 during a high-level period (shift period) of the clock pulse ck1 and then is held by the clock inverter 102 and the inverter 103 during a high-level period (hold period) of the clock pulse ck1x, whereby the pulse st1 is shifted as an output pulse out1 to the next shift stage.
In the conventional shift register mentioned above as an example, each of the clock inverters 101 and 102 constituting a basic circuit includes many elements as four transistors between the power supplies VDD and VSS, and if the transistor size is enlarged for shortening the rise time or fall time of the shift pulse waveform, the input gate capacitance of each shift stage is increased, so that the transistor size needs to be more enlarged to enhance the driving capability for enabling the preceding shift stage to drive, whereby a faster operation of the shift register fails to be attained.
Further, there exists another problem that the performance is prone to be affected by variations in the threshold voltage Vth of each transistor, and it becomes difficult to lower the required supply voltage due to the threshold voltage Vth of the transistor itself. Assuming now that, for example, the threshold voltage Vth of the PchMOS transistor is 2.5V or so and the threshold voltage Vth of the NchMOS transistor is 1.0V to 1.5V or so, then the positive-side circuit starts an operation at 2.0V to 3.0V or so, while the negative-side circuit starts an operation at 5V or so, hence raising a further problem with regard to the operational symmetry on the positive and negative sides.